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A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Springer, Berlin, Heidelberg, September 2006
Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
The data shown below were compiled from readership statistics for 4 Mendeley readers of this research output. Click here to see the associated Mendeley record.
|Readers by professional status||Count||As %|
|Professor > Associate Professor||2||50%|
|Student > Ph. D. Student||1||25%|
|Readers by discipline||Count||As %|