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| Chapter title |
Introduction
|
|---|---|
| Chapter number | 1 |
| Book title |
Verification Methodology Manual for SystemVerilog
|
| Published by |
Springer, Boston, MA, January 2006
|
| DOI | 10.1007/0-387-25556-7_1 |
| Book ISBNs |
978-0-387-25538-5, 978-0-387-25556-9
|