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Chapter title |
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap
|
---|---|
Chapter number | 59 |
Book title |
VLSI Design and Test
|
Published by |
Springer, Singapore, July 2019
|
DOI | 10.1007/978-981-32-9767-8_59 |
Book ISBNs |
978-9-81-329766-1, 978-9-81-329767-8
|
Authors |
Venkata Appa Rao Yempada, Srivatsava Jandhyala, Yempada, Venkata Appa Rao, Jandhyala, Srivatsava |