Transactions on High-Performance Embedded Architectures and Compilers IV

Chapter 1 A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

Chapter 2 Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces

Chapter 3 Compiler Directed Issue Queue Energy Reduction

Chapter 4 A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors

Chapter 5 Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors

Chapter 6 A Highly Scalable Parallel Implementation of H.264

Chapter 7 Communication Based Proactive Link Power Management

Chapter 8 Finding Extreme Behaviors in Microprocessor Workloads

Chapter 9 Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

Chapter 10 Transactions on High-Performance Embedded Architectures and Compilers IV

Chapter 11 A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture

Chapter 12 A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

Chapter 13 Software Transactional Memory Validation – Time and Space Considerations

Chapter 14 Tiled Multi-Core Stream Architecture

Chapter 15 An Efficient and Flexible Task Management for Many Cores

Chapter 16 On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –

Chapter 17 Advanced Packet Segmentation and Buffering Algorithms in Network Processors

Chapter 18 Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation

Chapter 19 A Cost Model for Partial Dynamic Reconfiguration

Chapter 20 Heterogeneous Design in Functional DIF

Chapter 21 Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration