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Transactions on High-Performance Embedded Architectures and Compilers IV

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Cover of 'Transactions on High-Performance Embedded Architectures and Compilers IV'

Table of Contents

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    Book Overview
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    Chapter 1 A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors
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    Chapter 2 Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces
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    Chapter 3 Compiler Directed Issue Queue Energy Reduction
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    Chapter 4 A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors
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    Chapter 5 Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors
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    Chapter 6 A Highly Scalable Parallel Implementation of H.264
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    Chapter 7 Communication Based Proactive Link Power Management
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    Chapter 8 Finding Extreme Behaviors in Microprocessor Workloads
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    Chapter 9 Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
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    Chapter 10 Transactions on High-Performance Embedded Architectures and Compilers IV
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    Chapter 11 A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture
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    Chapter 12 A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM
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    Chapter 13 Software Transactional Memory Validation – Time and Space Considerations
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    Chapter 14 Tiled Multi-Core Stream Architecture
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    Chapter 15 An Efficient and Flexible Task Management for Many Cores
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    Chapter 16 On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –
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    Chapter 17 Advanced Packet Segmentation and Buffering Algorithms in Network Processors
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    Chapter 18 Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation
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    Chapter 19 A Cost Model for Partial Dynamic Reconfiguration
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    Chapter 20 Heterogeneous Design in Functional DIF
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    Chapter 21 Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration
Attention for Chapter 21: Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration
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Chapter title
Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration
Chapter number 21
Book title
Transactions on High-Performance Embedded Architectures and Compilers IV
Published by
Springer, Berlin, Heidelberg, January 2011
DOI 10.1007/978-3-642-24568-8_21
Book ISBNs
978-3-64-224567-1, 978-3-64-224568-8
Authors

Stanley Jaddoe, Mark Thompson, Andy D. Pimentel

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 7 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Finland 1 14%
Estonia 1 14%
Unknown 5 71%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 2 29%
Student > Doctoral Student 1 14%
Professor 1 14%
Student > Bachelor 1 14%
Professor > Associate Professor 1 14%
Other 1 14%
Readers by discipline Count As %
Computer Science 6 86%
Engineering 1 14%