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Cryptographic Hardware and Embedded Systems - CHES 2007
Overview of attention for book
Table of Contents
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Book Overview
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Chapter 1
A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter
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Chapter 2
Gaussian Mixture Models for Higher-Order Side Channel Analysis
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Chapter 3
Side Channel Cryptanalysis of a Higher Order Masking Scheme
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Chapter 4
High-Speed True Random Number Generation with Logic Gates Only
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Chapter 5
FPGA Intrinsic PUFs and Their Use for IP Protection
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Chapter 6
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
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Chapter 7
Masking and Dual-Rail Logic Don’t Add Up
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Chapter 8
DPA-Resistance Without Routing Constraints?
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Chapter 9
On the Power of Bitslice Implementation on Intel Core2 Processor
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Chapter 10
Highly Regular Right-to-Left Algorithms for Scalar Multiplication
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Chapter 11
MAME: A Compression Function with Reduced Hardware Requirements
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Chapter 12
Collision Attacks on AES-Based MAC: Alpha-MAC
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Chapter 13
Secret External Encodings Do Not Prevent Transient Fault Analysis
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Chapter 14
Two New Techniques of Side-Channel Cryptanalysis
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Chapter 15
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
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Chapter 16
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
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Chapter 17
Arithmetic Operators for Pairing-Based Cryptography
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Chapter 18
FPGA Design of Self-certified Signature Verification on Koblitz Curves
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Chapter 19
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
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Chapter 20
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
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Chapter 21
Power Analysis Resistant AES Implementation with Instruction Set Extensions
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Chapter 22
Power and EM Attacks on Passive $13.56\,\textrm{MHz}$ RFID Devices
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Chapter 23
RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
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Chapter 24
RF-DNA: Radio-Frequency Certificates of Authenticity
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Chapter 25
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
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Chapter 26
Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA
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Chapter 27
A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations
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Chapter 28
Differential Behavioral Analysis
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Chapter 29
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
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Chapter 30
On the Implementation of a Fast Prime Generation Algorithm
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Chapter 31
PRESENT: An Ultra-Lightweight Block Cipher
Attention for Chapter 20:
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
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Mentioned by
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Book overview
1. A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter
2. Gaussian Mixture Models for Higher-Order Side Channel Analysis
3. Side Channel Cryptanalysis of a Higher Order Masking Scheme
4. High-Speed True Random Number Generation with Logic Gates Only
5. FPGA Intrinsic PUFs and Their Use for IP Protection
6. Evaluation of the Masked Logic Style MDPL on a Prototype Chip
7. Masking and Dual-Rail Logic Don’t Add Up
8. DPA-Resistance Without Routing Constraints?
9. On the Power of Bitslice Implementation on Intel Core2 Processor
10. Highly Regular Right-to-Left Algorithms for Scalar Multiplication
11. MAME: A Compression Function with Reduced Hardware Requirements
12. Collision Attacks on AES-Based MAC: Alpha-MAC
13. Secret External Encodings Do Not Prevent Transient Fault Analysis
14. Two New Techniques of Side-Channel Cryptanalysis
15. AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
16. Multi-gigabit GCM-AES Architecture Optimized for FPGAs
17. Arithmetic Operators for Pairing-Based Cryptography
18. FPGA Design of Self-certified Signature Verification on Koblitz Curves
19. How to Maximize the Potential of FPGA Resources for Modular Exponentiation
20. TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
21. Power Analysis Resistant AES Implementation with Instruction Set Extensions
22. Power and EM Attacks on Passive $13.56\,\textrm{MHz}$ RFID Devices
23. RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
24. RF-DNA: Radio-Frequency Certificates of Authenticity
25. CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
26. Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA
27. A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations
28. Differential Behavioral Analysis
29. Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
30. On the Implementation of a Fast Prime Generation Algorithm
31. PRESENT: An Ultra-Lightweight Block Cipher
Summary
Patents
So far, Altmetric has seen
10
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External memory data integrity validation
Grant US-12216919-B2
United States of America
04 Feb 2025
Application JP-WO2024171317-A1
Japan
22 Aug 2024
External memory data integrity validation
Grant US-11861179-B2
United States of America
02 Jan 2024
Storage of tree data structures
Grant US-11687592-B2
United States of America
27 Jun 2023
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