↓ Skip to main content

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

Overview of attention for article published in IEEE Journal of Solid-State Circuits, January 2023
Altmetric Badge

About this Attention Score

  • In the top 25% of all research outputs scored by Altmetric
  • High Attention Score compared to outputs of the same age (89th percentile)
  • Good Attention Score compared to outputs of the same age and source (75th percentile)

Mentioned by

news
2 news outlets

Citations

dimensions_citation
8 Dimensions

Readers on

mendeley
15 Mendeley