Digital Logic Design Using Verilog

Table of Contents

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   Book Overview
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   Chapter 1 Introduction
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   Chapter 2 Combinational Logic Design (Part I)
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   Chapter 3 Combinational Logic Design (Part II)
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   Chapter 4 Combinational Design Guidelines
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   Chapter 5 Sequential Logic Design
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   Chapter 6 Sequential Design Guidelines
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   Chapter 7 Complex Designs Using Verilog RTL
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   Chapter 8 Finite State Machines
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    Chapter 9 Simulation Concepts and PLD-Based Designs
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    Chapter 10 ASIC RTL Synthesis
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    Chapter 11 Static Timing Analysis
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    Chapter 12 Constraining ASIC Design
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    Chapter 13 Multiple Clock Domain Design
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    Chapter 14 Low Power Design
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    Chapter 15 System on Chip (SOC) Design