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Formal Semantics and Proof Techniques for Optimizing VHDL Models

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Cover of 'Formal Semantics and Proof Techniques for Optimizing VHDL Models'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 Related Work
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    Chapter 3 The Static Model
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    Chapter 4 A Well-Formed VHDL Model
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    Chapter 5 The Reduction Algebra
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    Chapter 6 Completeness of the Reduced Form
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    Chapter 7 Interval Temporal Logic
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    Chapter 8 The Dynamic Model
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    Chapter 9 Applications of the Dynamic Model
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    Chapter 10 A Framework for Proving Equivalences using PVS
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    Chapter 11 Conclusions
Attention for Chapter 4: A Well-Formed VHDL Model
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