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Mendeley readers
Chapter title |
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
|
---|---|
Chapter number | 91 |
Book title |
Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing
|
Published by |
Springer, Berlin, Heidelberg, August 2000
|
DOI | 10.1007/3-540-44614-1_91 |
Book ISBNs |
978-3-54-067899-1, 978-3-54-044614-9
|
Authors |
Bogdan Mătăsaru, Tudor Jebelean |
Mendeley readers
The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 2 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Student > Postgraduate | 1 | 50% |
Unknown | 1 | 50% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 1 | 50% |
Unknown | 1 | 50% |