Network-on-Chip Architectures

Chapter 2 A Baseline NoC Architecture

Chapter 3 ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

Chapter 4 RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]

Chapter 5 Exploring FaultoTolerant Network-on-Chip Architectures [37]

Chapter 6 On the Effects of Process Variation in Network-on-Chip Architectures [45]

Chapter 7 The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

Chapter 8 Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]

Chapter 9 A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

Chapter 10 Digest of Additional NoC MACRO-Architectural Research

Chapter 11 Conclusions and Future Work