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High Performance Embedded Architectures and Compilers

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Table of Contents

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    Book Overview
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    Chapter 1 Supercomputing for the Future, Supercomputing from the Past (Keynote)
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    Chapter 2 MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing
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    Chapter 3 rMPI: Message Passing on Multicore Processors with On-Chip Interconnect
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    Chapter 4 Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE
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    Chapter 5 BRAM-LUT Tradeoff on a Polymorphic DES Design
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    Chapter 6 Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
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    Chapter 7 Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP
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    Chapter 8 Fast Bounds Checking Using Debug Register
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    Chapter 9 Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis
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    Chapter 10 An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems
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    Chapter 11 Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions
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    Chapter 12 Experiences with Parallelizing a Bio-informatics Program on the Cell BE
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    Chapter 13 Drug Design Issues on the Cell BE
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    Chapter 14 Coffee : COmpiler Framework for Energy-Aware Exploration
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    Chapter 15 Integrated CPU Cache Power Management in Multiple Clock Domain Processors
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    Chapter 16 Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation
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    Chapter 17 The Significance of Affectors and Affectees Correlations for Branch Prediction
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    Chapter 18 Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator
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    Chapter 19 LPA: A First Approach to the Loop Processor Architecture
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    Chapter 20 Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm
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    Chapter 21 Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy
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    Chapter 22 Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior
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    Chapter 23 MLP-Aware Dynamic Cache Partitioning
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    Chapter 24 Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture
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    Chapter 25 Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory
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    Chapter 26 Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache
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High Performance Embedded Architectures and Compilers
Published by
Springer Berlin Heidelberg, January 2008
DOI 10.1007/978-3-540-77560-7
978-3-54-077559-1, 978-3-54-077560-7

Stenström, Per, Dubois, Michel, Katevenis, Manolis, Gupta, Rajiv, Ungerer, Theo

Mendeley readers

The data shown below were compiled from readership statistics for 4 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Germany 1 25%
Portugal 1 25%
Switzerland 1 25%
Belgium 1 25%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 7 175%
Student > Master 3 75%
Professor 1 25%
Student > Bachelor 1 25%
Professor > Associate Professor 1 25%
Other 0 0%
Readers by discipline Count As %
Computer Science 10 250%
Engineering 3 75%