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VLSI-SoC: Internet of Things Foundations

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Cover of 'VLSI-SoC: Internet of Things Foundations'

Table of Contents

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    Book Overview
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    Chapter 1 Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip
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    Chapter 2 Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
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    Chapter 3 Design and Optimization of Multiple-Mesh Clock Network
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    Chapter 4 Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture
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    Chapter 5 Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths
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    Chapter 6 VLSI-SoC: Internet of Things Foundations
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    Chapter 7 VLSI-SoC: Internet of Things Foundations
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    Chapter 8 Statistical Evaluation of Digital Techniques for $$\varSigma \varDelta $$ ADC BIST
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    Chapter 9 VLSI-SoC: Internet of Things Foundations
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    Chapter 10 VLSI-SoC: Internet of Things Foundations
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    Chapter 11 Transmission Channel Noise Aware Energy Effective LDPC Decoding
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    Chapter 12 VLSI-SoC: Internet of Things Foundations
Attention for Chapter 2: Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
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Chapter title
Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
Chapter number 2
Book title
VLSI-SoC: Internet of Things Foundations
Published by
Springer, Cham, October 2014
DOI 10.1007/978-3-319-25279-7_2
Book ISBNs
978-3-31-925278-0, 978-3-31-925279-7
Authors

Sreenivaas S. Muthyala, Nur A. Touba, Muthyala, Sreenivaas S., Touba, Nur A.

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