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Designing 2D and 3D Network-on-Chip Architectures

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Attention for Chapter 8: Middleware Memory Management in NoC
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Chapter title
Middleware Memory Management in NoC
Chapter number 8
Book title
Designing 2D and 3D Network-on-Chip Architectures
Published by
Springer, New York, NY, January 2014
DOI 10.1007/978-1-4614-4274-5_8
Book ISBNs
978-1-4614-4273-8, 978-1-4614-4274-5
Authors

Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch