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Mendeley readers
| Chapter title |
Verilog (Part 2)
|
|---|---|
| Chapter number | 8 |
| Book title |
Introduction to Logic Circuits & Logic Design with Verilog
|
| Published by |
Springer, Cham, January 2017
|
| DOI | 10.1007/978-3-319-53883-9_8 |
| Book ISBNs |
978-3-31-953882-2, 978-3-31-953883-9
|
| Authors |
Brock J. LaMeres |
Mendeley readers
The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
| Country | Count | As % |
|---|---|---|
| Unknown | 2 | 100% |
Demographic breakdown
| Readers by professional status | Count | As % |
|---|---|---|
| Unknown | 2 | 100% |
| Readers by discipline | Count | As % |
|---|---|---|
| Agricultural and Biological Sciences | 1 | 50% |
| Unknown | 1 | 50% |