Analog Circuit Design

Chapter 1 Speed-Power-Accuracy Trade-off In high-speed Analog-to-digital converters: Now and in the future...

Chapter 2 A Dual Mode 700 MSamples/s 6-bit, 200MSamples/s 7-bit A/D Converter in 0.25 Micron Digital CMOS

Chapter 3 A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Chapter 4 A 10-bit, 20–30 MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist

Chapter 5 A 2.5MHz Output-Rate Delta-Sigma ADC with 90dB SNR and 102dB SFDR

Chapter 6 A 13-bit bandpass sigma delta modulator for 10.7MHz digital IF with a 40MHz sampling rate

Chapter 7 System-Level Design Issues for Mixed-Signal ICs and Telecom Frontends

Chapter 8 Mixed Signal Design — Design Issues —

Chapter 9 Top-Down Design of Mixed-Signal Circuits

Chapter 10 Computer Aided Design for Integrated Systems

Chapter 11 Mixed Mode Sigma-Delta ADC Design for High Quality Audio

Chapter 12 Mixed-Mode Telecom Design

Chapter 13 On Placing Multiple Inductor-Based VCOs on the Same Mixed-Signal Substrate

Chapter 14 Fully Integrated CMOS Frequency Synthesizers for Wireless Communications

Chapter 15 Design and Optimization of RFCMOS-Circuits for Integrated PLL’s and Synthesizers

Chapter 17 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Chapter 18 Low Power Circuits for RF-Frequency Synthesizers in the Low GHz Range

Chapter 19 Erratum to: Design and Optimization of RFCMOS-Circuits for Integrated PLL’s and Synthesizers