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Mendeley readers
| Chapter title |
Formal Verification and Models
|
|---|---|
| Chapter number | 21 |
| Book title |
SVA: The Power of Assertions in SystemVerilog
|
| Published by |
Springer, Cham, January 2015
|
| DOI | 10.1007/978-3-319-07139-8_21 |
| Book ISBNs |
978-3-31-907138-1, 978-3-31-907139-8
|
| Authors |
Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny, Cerny, Eduard, Dudani, Surrendra, Havlicek, John, Korchemny, Dmitry |
Mendeley readers
The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
| Country | Count | As % |
|---|---|---|
| Unknown | 1 | 100% |
Demographic breakdown
| Readers by professional status | Count | As % |
|---|---|---|
| Student > Ph. D. Student | 1 | 100% |
| Readers by discipline | Count | As % |
|---|---|---|
| Computer Science | 1 | 100% |