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Mendeley readers
Chapter title |
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
|
---|---|
Chapter number | 28 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2011
|
DOI | 10.1007/978-3-642-24154-3_28 |
Book ISBNs |
978-3-64-224153-6, 978-3-64-224154-3
|
Authors |
Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen, Rahmani, Amir-Mohammad, Vaddina, Kameswar Rao, Liljeberg, Pasi, Plosila, Juha, Tenhunen, Hannu |
Mendeley readers
The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 3 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Researcher | 1 | 33% |
Unknown | 2 | 67% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 1 | 33% |
Unknown | 2 | 67% |