Correct Hardware Design and Verification Methods

Table of Contents

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   Book Overview
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   Chapter 1 View from the Fringe of the Fringe
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   Chapter 2 Hardware Synthesis Using SAFL and Application to Processor Design
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   Chapter 3 Applications of Hierarchical Verification in Model Checking
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   Chapter 4 Pruning Techniques for the SAT-Based Bounded Model Checking Problem
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   Chapter 5 Heuristics for Hierarchical Partitioning with Application to Model Checking
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   Chapter 6 Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs
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   Chapter 7 Deriving Real-Time Programs from Duration Calculus Specifications
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   Chapter 8 Reproducing Synchronization Bugs with Model Checking
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    Chapter 9 Formally-Based Design Evaluation
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    Chapter 10 Multiclock Esterel
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    Chapter 11 Register Transformations with Multiple Clock Domains
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    Chapter 12 Temporal Properties of Self-Timed Rings
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    Chapter 13 Coverability Analysis Using Symbolic Model Checking
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    Chapter 14 Correct Hardware Design and Verification Methods
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    Chapter 15 Formal Pipeline Design
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    Chapter 16 Verification of Basic Block Schedules Using RTL Transformations
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    Chapter 17 Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
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    Chapter 18 Proof Engineering in the Large: Formal Verification of Pentium®4 Floating-Point Divider
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    Chapter 19 Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
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    Chapter 20 A Higher-Level Language for Hardware Synthesis
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    Chapter 21 Hierarchical Verification Using an MDG-HOL Hybrid Tool
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    Chapter 22 Exploiting Transition Locality in Automatic Verification
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    Chapter 23 Efficient Debugging in a Formal Verification Environment
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    Chapter 24 Using Combinatorial Optimization Methods for Quantification Scheduling
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    Chapter 25 Net Reductions for LTL Model-Checking
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    Chapter 26 Formal Verification of the VAMP Floating Point Unit
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    Chapter 27 A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® Itanium™ Processor Bus Protocol
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    Chapter 28 The Design and Verification of a Sorter Core
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    Chapter 29 Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip
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    Chapter 30 Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation
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    Chapter 31 Formal Verification of Conflict Detection Algorithms
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    Chapter 32 Induction-Oriented Formal Verification in Symmetric Interconnection Networks
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    Chapter 33 A Framework for Microprocessor Correctness Statements
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    Chapter 34 From Operational Semantics to Denotational Semantics for Verilog
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    Chapter 35 Efficient Verification of a Class of Linear Hybrid Automata Using Linear Programming