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Mendeley readers
Chapter title |
Design of Power-Efficient 5- to 32-Row Decoder for 1 KB SRAM Using VLSI Technology
|
---|---|
Chapter number | 59 |
Book title |
Computing in Engineering and Technology
|
Published by |
Springer, Singapore, January 2020
|
DOI | 10.1007/978-981-32-9515-5_59 |
Book ISBNs |
978-9-81-329514-8, 978-9-81-329515-5
|
Authors |
A. K. Pathrikar, Rajkumar S. Deshpande, Pathrikar, A. K., Deshpande, Rajkumar S. |
Mendeley readers
The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 1 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor | 1 | 100% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 1 | 100% |