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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Springer Berlin Heidelberg

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Connecting E-Dreams to Deep-Submicron Realities
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    Chapter 2 Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization
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    Chapter 3 Low-Voltage Embedded RAMs – Current Status and Future Trends
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    Chapter 4 Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing
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    Chapter 5 Leakage in CMOS Circuits – An Introduction
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    Chapter 6 The Certainty of Uncertainty: Randomness in Nanometer Design
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    Chapter 7 Crosstalk Cancellation for Realistic PCB Buses
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    Chapter 8 A Low-Power Encoding Scheme for GigaByte Video Interfaces
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    Chapter 9 Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures
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    Chapter 10 Perfect 3-Limited-Weight Code for Low Power I/O
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    Chapter 11 A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses
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    Chapter 12 Performance Metric Based Optimization Protocol
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    Chapter 13 Temperature Dependence in Low Power CMOS UDSM Process
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    Chapter 14 Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques
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    Chapter 15 High Yield Standard Cell Libraries: Optimization and Modeling
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    Chapter 16 A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits
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    Chapter 17 Sleepy Stack Reduction of Leakage Power
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    Chapter 18 A Cycle-Accurate Energy Estimator for CMOS Digital Circuits
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    Chapter 19 Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures
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    Chapter 20 Reducing Cross-Talk Induced Power Consumption and Delay
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    Chapter 21 Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
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    Chapter 22 Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
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    Chapter 23 Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS
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    Chapter 24 Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications
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    Chapter 25 Register Isolation for Synthesizable Register Files
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    Chapter 26 Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures
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    Chapter 27 Design of High-Speed Low-Power Parallel-Prefix VLSI Adders
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    Chapter 28 GALSification of IEEE 802.11a Baseband Processor
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    Chapter 29 TAST Profiler and Low Energy Asynchronous Design Methodology
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    Chapter 30 Low Latency Synchronization Through Speculation
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    Chapter 31 Minimizing the Power Consumption of an Asynchronous Multiplier
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    Chapter 32 A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling
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    Chapter 33 L0 Cluster Synthesis and Operation Shuffling
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    Chapter 34 On Combined DVS and Processor Evaluation
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    Chapter 35 A Multi-level Validation Methodology for Wireless Network Applications
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    Chapter 36 SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
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    Chapter 37 Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards
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    Chapter 38 Towards a Software Power Cost Analysis Framework Using Colored Petri Net
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    Chapter 39 A 260ps Quasi-static ALU in 90nm CMOS
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    Chapter 40 Embedded EEPROM Speed Optimization Using System Power Supply Resources
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    Chapter 41 Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption
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    Chapter 42 A Predictive Synchronizer for Periodic Clock Domains
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    Chapter 43 Power Supply Net for Adiabatic Circuits
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    Chapter 44 A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
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    Chapter 45 Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery
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    Chapter 46 An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design
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    Chapter 47 Wirelength Reduction Using 3-D Physical Design
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    Chapter 48 On Skin Effect in On-Chip Interconnects
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    Chapter 49 A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits
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    Chapter 50 A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors
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    Chapter 51 A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design
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    Chapter 52 The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems
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    Chapter 53 Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems
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    Chapter 54 PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
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    Chapter 55 Power Consumption of Performance-Scaled SIMD Processors
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    Chapter 56 Low Effort, High Accuracy Network-on-Chip Power Macro Modeling
  58. Altmetric Badge
    Chapter 57 Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling
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    Chapter 58 Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers
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    Chapter 59 Power Aware Dividers in FPGA
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    Chapter 60 A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
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    Chapter 61 The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms
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    Chapter 62 Low Power Co-design Tool and Power Optimization of Schedules and Memory System
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    Chapter 63 Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform
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    Chapter 64 Enhancing GALS Processor Performance Using Data Classification Based on Data Latency
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    Chapter 65 Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
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    Chapter 66 Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems
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    Chapter 67 Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path
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    Chapter 68 Power Estimation for Ripple-Carry Adders with Correlated Input Data
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    Chapter 69 LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS
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    Chapter 70 Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits
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    Chapter 71 A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic
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    Chapter 72 Pipelines in Dynamic Dual-Rail Circuits
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    Chapter 73 Optimum Buffer Size for Dynamic Voltage Processors
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    Chapter 74 Design Optimization with Automated Cell Generation
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    Chapter 75 A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool
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    Chapter 76 A Novel Constant-Time Fault-Secure Binary Counter
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    Chapter 77 Buffer Sizing for Crosstalk Induced Delay Uncertainty
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    Chapter 78 Optimal Logarithmic Representation in Terms of SNR Behavior
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    Chapter 79 A New Logic Transformation Method for Both Low Power and High Testability
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    Chapter 80 Energy-Efficient Hardware Architecture for Variable N-point 1D DCT
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    Chapter 81 Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits
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    Chapter 82 A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment
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    Chapter 83 Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis
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    Chapter 84 On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects
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    Chapter 85 Signal Sampling Based Transition Modeling for Digital Gates Characterization
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    Chapter 86 Physical Extension of the Logical Effort Model
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    Chapter 87 An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
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    Chapter 88 Moment-Based Estimation of Switching Activity for Correlated Distributions
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    Chapter 89 Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
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    Chapter 90 A Physically Oriented Model to Quantify the Noise-on-Delay Effect
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    Chapter 91 Noise Margin in Low Power SRAM Cells
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    Chapter 92 Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
Attention for Chapter 12: Performance Metric Based Optimization Protocol
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