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Chapter title |
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures
|
---|---|
Chapter number | 9 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2004
|
DOI | 10.1007/978-3-540-30205-6_9 |
Book ISBNs |
978-3-54-023095-3, 978-3-54-030205-6
|
Authors |
Markus Tahedl, Hans-Jörg Pfleiderer |