Table of Contents

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   Book Overview
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   Chapter 1 Two ASIC for Low and Middle Levels of Real Time Image Processing
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   Chapter 2 64 × 64 Pixels General Purpose Digital Vision Chip
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   Chapter 3 A vision system on chip for industrial control
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   Chapter 4 Fast Recursive Implementation of the Gaussian Filter
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   Chapter 5 A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals
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   Chapter 6 Dynamically Reconfigurable Architectures for Digital Signal Processing Applications
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   Chapter 7 Reconfigurable Architecture Using High Speed FPGA
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   Chapter 8 Design Technology for Systems-on-Chip
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    Chapter 9 Distributed Collaborative Design over Cave2 Framework
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    Chapter 10 High Performance Java Hardware Engine and Software Kernel for Embedded Systems
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    Chapter 11 An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures
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    Chapter 12 Interconnect Capacitance Modelling in a VDSM CMOS Technology
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    Chapter 13 Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design
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    Chapter 14 An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms
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    Chapter 15 Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µ m Bulk and Silicon-On-Insulator CMOS Technologies
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    Chapter 16 A Standardized Co-simulation Backbone
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    Chapter 17 Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory
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    Chapter 18 Modeling Power Dynamics for an Embedded DSP Processor Core
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    Chapter 19 Power Consumption Model for the DSP OAK Processor
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    Chapter 20 Integration of Robustness in the Design of a Cell
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    Chapter 21 Impact of Technology Spreading on MEMS design Robustness
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    Chapter 22 A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
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    Chapter 23 Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder
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    Chapter 24 Low-Voltage Embedded-RAM Technology: Present and Future
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    Chapter 25 Low-Voltage 0.25 µ m CMOS Improved Power Adaptive Issue Queue For Embedded Microprocessors
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    Chapter 26 Gate sizing for low power design
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    Chapter 27 Modeling and design of asynchronous priority arbiters for on-chip communication systems
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    Chapter 28 Feasible delay bound definition
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    Chapter 29 CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors
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    Chapter 30 A VHDL-AMS Case Study
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    Chapter 31 Speeding Up Verification of RTL Designs by Computing One-to-One Abstractions with Reduced Signal Widths
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    Chapter 32 Functional Test Generation Using Constraint Logic Programming
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    Chapter 33 An Industrial Approach to Core-Based System Chip Testing
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    Chapter 34 Power-constrained Test Scheduling for SoCs under a “no session” scheme
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    Chapter 35 Random Adjacent Sequences
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    Chapter 36 On-chip generator of a saw-tooth test stimulus for ADC BIST
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    Chapter 37 Built-in test of analog non-linear circuits in a SOC environment
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    Chapter 38 Design of a Fast CMOS APS Imager for High Speed Laser Detections
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    Chapter 39 Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing
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    Chapter 40 Erratum to: SOC Design Methodologies