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Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings

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Cover of 'Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings'

Table of Contents

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    Book Overview
  2. Altmetric Badge
    Chapter 1 The Age of Adaptive Computing Is Here
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    Chapter 2 Disruptive Trends by Data-Stream-Based Computing
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    Chapter 3 Multithreading for Logic-Centric Systems
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    Chapter 4 Fast Prototyping with Co-operation of Simulation and Emulation
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    Chapter 5 How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project
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    Chapter 6 Implementing Asynchronous Circuits on LUT Based FPGAs
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    Chapter 7 A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
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    Chapter 8 Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
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    Chapter 9 iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
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    Chapter 10 Field-Programmable Custom Computing Machines - A Taxonomy -
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    Chapter 11 Embedded Reconfigurable Logic Core for DSP Applications
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    Chapter 12 Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
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    Chapter 13 FPGA QAM Demodulator Design
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    Chapter 14 Analytical Framework for Switch Block Design
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    Chapter 15 Modular, Fabric-Specific Synthesis for Programmable Architectures
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    Chapter 16 On Optimum Designs of Universal Switch Blocks
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    Chapter 17 Improved Functional Simulation of Dynamically Reconfigurable Logic
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    Chapter 18 Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology
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    Chapter 19 Dynamic Reconfiguration in Mobile Systems
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    Chapter 20 Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
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    Chapter 21 Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
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    Chapter 22 Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
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    Chapter 23 FPGA Implementation of the Wavelet Packet Transform for High Speed Communications
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    Chapter 24 A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™
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    Chapter 25 Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
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    Chapter 26 Rapid and Reliable Routability Estimation for FPGAs
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    Chapter 27 Integrated Iterative Approach to FPGA Placement
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    Chapter 28 TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
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    Chapter 29 High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
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    Chapter 30 High Speed Homology Search Using Run-Time Reconfiguration
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    Chapter 31 Partially Reconfigurable Cores for Xilinx Virtex
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    Chapter 32 On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
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    Chapter 33 A Flexible Power Model for FPGAs
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    Chapter 34 Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
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    Chapter 35 Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor
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    Chapter 36 A Tool for Activity Estimation in FPGAs
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    Chapter 37 FSM Decomposition for Low Power in FPGA
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    Chapter 38 Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
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    Chapter 39 A Prolog-Based Hardware Development Environment
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    Chapter 40 Fly — A Modifiable Hardware Compiler
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    Chapter 41 Challenges and Opportunities for FPGA Platforms
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    Chapter 42 Design and Implementation of FPGA Circuits for High Speed Network Monitors
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    Chapter 43 Granidt: Towards Gigabit Rate Network Intrusion Detection Technology
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    Chapter 44 Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
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    Chapter 45 Field-Programmable Analog Arrays: A Floating—Gate Approach
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    Chapter 46 A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
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    Chapter 47 A Framework for Teaching (Re)Configurable Architectures in Student Projects
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    Chapter 48 Specialized Hardware for Deep Network Packet Filtering
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    Chapter 49 Implementation of a Successive Erasure BCH (16,7,6) Decoder and Performance Simulation by Rapid Prototyping
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    Chapter 50 Fast RNS FPL-based Communications Receiver Design and Implementation
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    Chapter 51 UltraSONIC: A Reconfigurable Architecture for Video Image Processing
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    Chapter 52 Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
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    Chapter 53 Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
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    Chapter 54 Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
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    Chapter 55 Automating Customisation of Floating-Point Designs
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    Chapter 56 Energy-Efficient Matrix Multiplication on FPGAs
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    Chapter 57 Run-Time Adaptive Flexible Instruction Processors
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    Chapter 58 DARP — A Digital Audio Reconfigurable Processor
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    Chapter 59 System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
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    Chapter 60 An FPGA Based SHA-256 Processor
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    Chapter 61 Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
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    Chapter 62 On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
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    Chapter 63 Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
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    Chapter 64 Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
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    Chapter 65 Logarithmic Number System and Floating-Point Arithmetics on FPGA
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    Chapter 66 Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
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    Chapter 67 Morphable Multipliers
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    Chapter 68 A Library of Parameterized Floating-Point Modules and Their Use
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    Chapter 69 Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
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    Chapter 70 An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms
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    Chapter 71 Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
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    Chapter 72 Efficient Metacomputation Using Self-Reconfiguration
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    Chapter 73 An FPGA Co-processor for Real-Time Visual Tracking
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    Chapter 74 Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware
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    Chapter 75 Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
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    Chapter 76 Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
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    Chapter 77 Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2 m )
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    Chapter 78 6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
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    Chapter 79 Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
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    Chapter 80 A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
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    Chapter 81 Creating a World of Smart Re-configurable Devices
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    Chapter 82 Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
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    Chapter 83 Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
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    Chapter 84 The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
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    Chapter 85 An FPGA Implementation of a Multi-comparand Multi-search Associative Processor
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    Chapter 86 AES Implementation on FPGA: Time - Flexibility Tradeoff
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    Chapter 87 An FPGA Implementation of the Linear Cryptanalysis
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    Chapter 88 Compiling Application-Specific Hardware
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    Chapter 89 XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
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    Chapter 90 Sea Cucumber: A Synthesizing Compiler for FPGAs
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    Chapter 91 Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
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    Chapter 92 Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs
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    Chapter 93 High Performance Quadrature Digital Mixers for FPGAs
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    Chapter 94 HAGAR: Efficient Multi-context Graph Processors
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    Chapter 95 Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
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    Chapter 96 On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach
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    Chapter 97 REFLIX: A Processor Core for Reactive Embedded Applications
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    Chapter 98 Factors Influencing the Performance of a CPU-RFU Hybrid Architecture
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    Chapter 99 Implementing Converters in FPLD
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    Chapter 100 A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
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    Chapter 101 Integration of Reconfigurable Hardware into System-Level Design
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    Chapter 102 A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
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    Chapter 103 The Integration of SystemC and Hardware-Assisted Verification
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    Chapter 104 Using Design Hierarchy to Improve Quality of Results in FPGAs
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    Chapter 105 Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
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    Chapter 106 A General Hardware Design Model for Multicontext FPGAs
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    Chapter 107 Dynamically Reconfigurable Hardware — A New Perspective for Neural Network Implementations
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    Chapter 108 A Compilation Framework for a Dynamically Reconfigurable Architecture
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    Chapter 109 Data Dependent Circuit for Subgraph Isomorphism Problem
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    Chapter 110 Exploration of Design Space in ECDSA
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    Chapter 111 2D and 3D Computer Graphics Algorithms under MORPHOSYS
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    Chapter 112 A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip
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    Chapter 113 SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor
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    Chapter 114 Real-Time Medical Diagnosis on a Multiple FPGA-based System
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    Chapter 115 Threshold Element-Based Symmetric Function Generators and Their Functional Extension
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    Chapter 116 Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
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    Chapter 117 Building Custom FIR Filters Using System Generator
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    Chapter 118 SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
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    Chapter 119 Dynamic Constant Coefficient Convolvers Implemented in FPGAs
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    Chapter 120 VIZARD II: An FPGA-based Interactive Volume Rendering System
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    Chapter 121 RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
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    Chapter 122 General Purpose Prototyping Platform for Data-Processor Research and Development
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    Chapter 123 High Speed Computation of Three Dimensional Cellular Automata with FPGA
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    Chapter 124 SOPC-based Embedded Smart Strain Gage Sensor
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    Chapter 125 Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
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    Chapter 126 An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
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    Chapter 127 FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms
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    Chapter 128 Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer
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    Chapter 129 A Novel Watermarking Technique for LUT Based FPGA Designs
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    Chapter 130 Implementing CSAT Local Search on FPGAs
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    Chapter 131 A Reconfigurable Processor Architecture
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    Chapter 132 A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor
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    Chapter 133 Gene Matching Using JBits
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    Chapter 134 Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
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    Chapter 135 A Placement/Routing Approach for FPGA Accelerators
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Title
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings
Published by
Springer Science & Business Media, August 2002
DOI 10.1007/3-540-46117-5
ISBNs
978-3-54-044108-3, 978-3-54-046117-3
Editors

Glesner, Manfred, Renovell, Michel, Zipf, Peter

Twitter Demographics

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Mendeley readers

The data shown below were compiled from readership statistics for 22 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
United Kingdom 1 5%
Ireland 1 5%
Germany 1 5%
Unknown 19 86%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 6 27%
Researcher 4 18%
Professor > Associate Professor 3 14%
Student > Doctoral Student 3 14%
Student > Master 2 9%
Other 4 18%
Readers by discipline Count As %
Engineering 9 41%
Computer Science 9 41%
Chemistry 2 9%
Social Sciences 1 5%
Business, Management and Accounting 1 5%
Other 0 0%