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Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
Springer, Cham, September 2016
Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione
The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.
|Readers by professional status||Count||As %|
|Readers by discipline||Count||As %|
|Arts and Humanities||1||100%|