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Power-Aware Computer Systems

Overview of attention for book
Cover of 'Power-Aware Computer Systems'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors
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    Chapter 2 Ramp Up/Down Functional Unit to Reduce Step Power
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    Chapter 3 An Adaptive Issue Queue for Reduced Power at High Performance
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    Chapter 4 Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform
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    Chapter 5 Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering
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    Chapter 6 Compiler-Directed Dynamic Frequency and Voltage Scheduling
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    Chapter 7 Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
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    Chapter 8 Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
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    Chapter 9 TEM 2 P 2 EST: A Thermal Enabled Multi-model Power/Performance ESTimator
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    Chapter 10 Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor
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    Chapter 11 A Comparison of Two Architectural Power Models
Attention for Chapter 2: Ramp Up/Down Functional Unit to Reduce Step Power
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3 Mendeley
Summary
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Chapter title
Ramp Up/Down Functional Unit to Reduce Step Power
Chapter number 2
Book title
Power-Aware Computer Systems
Published by
Springer, Berlin, Heidelberg, November 2000
DOI 10.1007/3-540-44572-2_2
Book ISBNs
978-3-54-042329-4, 978-3-54-044572-2
Authors

Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, Sam Nakagawa, Lei He

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 3 100%

Demographic breakdown

Readers by professional status Count As %
Student > Master 2 67%
Unknown 1 33%
Readers by discipline Count As %
Computer Science 1 33%
Unknown 2 67%

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