Low Power Networks-on-Chip

Chapter 1 Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

Chapter 2 Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

Chapter 3 Adaptive Voltage Control for Energy-Efficient NoC Links

Chapter 5 Application-Specific Routing Algorithms for Low Power Network on Chip Design

Chapter 6 Adaptive Data Compression for Low-Power On-Chip Networks

Chapter 7 Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

Chapter 8 Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Chapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study

Chapter 10 RF-Interconnect for Future Network-On-Chip