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Logic Synthesis and Verification

Overview of attention for book
Cover of 'Logic Synthesis and Verification'

Table of Contents

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    Book Overview
  2. Altmetric Badge
    Chapter 1 Two-Level Logic Minimization
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    Chapter 2 Multi-Level Logic Optimization
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    Chapter 3 Flexibility in Logic
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    Chapter 4 Multiple-Valued Logic Synthesis and Optimization
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    Chapter 5 Technology Mapping
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    Chapter 6 Technology-Based Transformations
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    Chapter 7 Logical and Physical Design: A Flow Perspective
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    Chapter 8 Logic Synthesis for Low Power
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    Chapter 9 Optimization of Synchronous Circuits
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    Chapter 10 Asynchronous Control Circuits
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    Chapter 11 Ordered Binary Decision Diagrams
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    Chapter 12 Sat and ATPG: Algorithms for Boolean Decision Problems
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    Chapter 13 Combinational and Sequential Equivalence Checking
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    Chapter 14 Static Timing Analysis
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    Chapter 15 The Future of Logic Synthesis and Verification
Attention for Chapter 1: Two-Level Logic Minimization
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Citations

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Summary Dimensions citations
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Chapter title
Two-Level Logic Minimization
Chapter number 1
Book title
Logic Synthesis and Verification
Published by
Springer, Boston, MA, January 2002
DOI 10.1007/978-1-4615-0817-5_1
Book ISBNs
978-1-4613-5253-2, 978-1-4615-0817-5
Authors

Olivier Coudert, Tsutomu Sasao, Coudert, Olivier, Sasao, Tsutomu

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Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 9 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 9 100%

Demographic breakdown

Readers by professional status Count As %
Researcher 4 44%
Student > Ph. D. Student 2 22%
Lecturer 1 11%
Unknown 2 22%
Readers by discipline Count As %
Computer Science 3 33%
Engineering 2 22%
Physics and Astronomy 1 11%
Agricultural and Biological Sciences 1 11%
Unknown 2 22%

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