Logic Synthesis and Verification

Table of Contents

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   Book Overview
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   Chapter 1 Two-Level Logic Minimization
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   Chapter 2 Multi-Level Logic Optimization
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   Chapter 3 Flexibility in Logic
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   Chapter 4 Multiple-Valued Logic Synthesis and Optimization
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   Chapter 5 Technology Mapping
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   Chapter 6 Technology-Based Transformations
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   Chapter 7 Logical and Physical Design: A Flow Perspective
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   Chapter 8 Logic Synthesis for Low Power
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    Chapter 9 Optimization of Synchronous Circuits
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    Chapter 10 Asynchronous Control Circuits
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    Chapter 11 Ordered Binary Decision Diagrams
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    Chapter 12 Sat and ATPG: Algorithms for Boolean Decision Problems
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    Chapter 13 Combinational and Sequential Equivalence Checking
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    Chapter 14 Static Timing Analysis
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    Chapter 15 The Future of Logic Synthesis and Verification