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Chapter title |
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
|
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Chapter number | 8 |
Book title |
System Level Design from HW/SW to Memory for Embedded Systems
|
Published by |
Springer, Cham, November 2015
|
DOI | 10.1007/978-3-319-90023-0_8 |
Book ISBNs |
978-3-31-990022-3, 978-3-31-990023-0
|
Authors |
Tayfun Gezgin, Björn Koopmann, Achim Rettberg, Gezgin, Tayfun, Koopmann, Björn, Rettberg, Achim |