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System Level Design from HW/SW to Memory for Embedded Systems

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Cover of 'System Level Design from HW/SW to Memory for Embedded Systems'

Table of Contents

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    Book Overview
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    Chapter 1 Ontological User Modeling for Ambient Assisted Living Service Personalization
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    Chapter 2 Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs
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    Chapter 3 Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study
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    Chapter 4 Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments
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    Chapter 5 Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving
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    Chapter 6 Timed Path Conditions in MATLAB/Simulink
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    Chapter 7 Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics
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    Chapter 8 Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
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    Chapter 9 Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems
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    Chapter 10 Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
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    Chapter 11 Modeling and Analysis of SLDL-Captured NoC Abstractions
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    Chapter 12 Taming the Memory Demand Complexity of Adaptive Vision Algorithms
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    Chapter 13 HMC and DDR Performance Trade-offs
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    Chapter 14 Managing Cache Memory Resources in Adaptive Many-Core Systems
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    Chapter 15 A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools
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    Chapter 16 Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables
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    Chapter 17 Low Latency FPGA Implementation of Izhikevich-Neuron Model
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    Chapter 18 Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
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