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VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

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Cover of 'VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability'

Table of Contents

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    Book Overview
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    Chapter 1 Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures
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    Chapter 2 Logic with Unipolar Memristors – Circuits and Design Methodology
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    Chapter 3 Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors
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    Chapter 4 Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
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    Chapter 5 Digital Hardware Design Based on Metamodels and Model Transformations
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    Chapter 6 Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings
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    Chapter 7 Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
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    Chapter 8 Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping
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    Chapter 9 Earth Mover’s Distance as a Comparison Metric for Analog Behavior
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    Chapter 10 Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO
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    Chapter 11 A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA
Attention for Chapter 7: Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
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