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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Springer, Berlin, Heidelberg

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 A Power-Efficient and Scalable Load-Store Queue Design
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    Chapter 2 Power Consumption Reduction Using Dynamic Control of Micro Processor Performance
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    Chapter 3 Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
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    Chapter 4 Dynamic Instruction Cascading on GALS Microprocessors
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    Chapter 5 Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width
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    Chapter 6 A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net
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    Chapter 7 Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory
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    Chapter 8 Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems
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    Chapter 9 Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications
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    Chapter 10 Systematic Preprocessing of Data Dependent Constructs for Embedded Systems
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    Chapter 11 Temperature Aware Datapath Scheduling
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    Chapter 12 Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform
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    Chapter 13 Improving the Memory Bandwidth Utilization Using Loop Transformations
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    Chapter 14 Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures
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    Chapter 15 Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming
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    Chapter 16 A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction
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    Chapter 17 An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments
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    Chapter 18 Energy-Aware System-on-Chip for 5 GHz Wireless LANs
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    Chapter 19 Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction
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    Chapter 20 An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
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    Chapter 21 Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques
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    Chapter 22 Power Consumption in Reversible Logic Addressed by a Ramp Voltage
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    Chapter 23 Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing
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    Chapter 24 Back Annotation in High Speed Asynchronous Design
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    Chapter 25 Optimization of Reliability and Power Consumption in Systems on a Chip
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    Chapter 26 Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs
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    Chapter 27 A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design
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    Chapter 28 Power Supply Selective Mapping for Accurate Timing Analysis
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    Chapter 29 Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses
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    Chapter 30 PSK Signalling on NoC Buses
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    Chapter 31 Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding
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    Chapter 32 Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
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    Chapter 33 Efficient Simulation of Power/Ground Networks with Package and Vias
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    Chapter 34 Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation
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    Chapter 35 Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates
  37. Altmetric Badge
    Chapter 36 Compact Static Power Model of Complex CMOS Gates
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    Chapter 37 Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model
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    Chapter 38 Statistical Critical Path Analysis Considering Correlations
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    Chapter 39 A CAD Platform for Sensor Interfaces in Low-Power Applications
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    Chapter 40 An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints
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    Chapter 41 Efficient Post-layout Power-Delay Curve Generation
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    Chapter 42 Power – Performance Optimization for Custom Digital Circuits
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    Chapter 43 Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs
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    Chapter 44 Logic-Level Fast Current Simulation for Digital CMOS Circuits
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    Chapter 45 Design of Variable Input Delay Gates for Low Dynamic Power Circuits
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    Chapter 46 Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications
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    Chapter 47 Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes
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    Chapter 48 Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs
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    Chapter 49 Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs
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    Chapter 50 Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology
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    Chapter 51 An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers
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    Chapter 52 Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers
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    Chapter 53 Low-Power Aspects of Nonlinear Signal Processing
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    Chapter 54 Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring
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    Chapter 55 Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives
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    Chapter 56 A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
  58. Altmetric Badge
    Chapter 57 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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    Chapter 58 A Method to Design Compact Dual-rail Asynchronous Primitives
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    Chapter 59 Enhanced GALS Techniques for Datapath Applications
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    Chapter 60 Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study
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    Chapter 61 Area-Aware Pipeline Gating for Embedded Processors
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    Chapter 62 Fast Low-Power 64-Bit Modular Hybrid Adder
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    Chapter 63 Speed Indicators for Circuit Optimization
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    Chapter 64 Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms
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    Chapter 65 Power-Clock Gating in Adiabatic Logic Circuits
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    Chapter 66 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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    Chapter 67 Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers
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    Chapter 68 Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures
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    Chapter 69 The Optimal Wire Order for Low Power CMOS
  71. Altmetric Badge
    Chapter 70 Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water
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    Chapter 71 Temperature Dependency in UDSM Process
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    Chapter 72 Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System
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    Chapter 73 A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor
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    Chapter 74 A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
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    Chapter 75 Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
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    Chapter 76 Tutorial Hearing Aid Algorithms
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    Chapter 77 Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids
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    Chapter 78 Optimization of Modules for Digital Audio Processing
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    Chapter 79 Traveling the Wild Frontier of Ultra Low-Power Design
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    Chapter 80 DLV (Deep Low Voltage): Circuits and Devices
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    Chapter 81 Wireless Sensor Networks: A New Life Paradigm
  83. Altmetric Badge
    Chapter 82 Cryptography: Circuits and Systems Approach
Attention for Chapter 71: Temperature Dependency in UDSM Process
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Chapter title
Temperature Dependency in UDSM Process
Chapter number 71
Book title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Berlin, Heidelberg, September 2005
DOI 10.1007/11556930_71
Book ISBNs
978-3-54-029013-1, 978-3-54-032080-7
Authors

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine, Lasbouygues, B., Wilson, Robin, Azémard, Nadine, Maurine, Philippe

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The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.
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Geographical breakdown

Country Count As %
Unknown 3 100%

Demographic breakdown

Readers by professional status Count As %
Student > Doctoral Student 2 67%
Researcher 1 33%
Readers by discipline Count As %
Engineering 2 67%
Computer Science 1 33%