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VLSI Design and Test

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Cover of 'VLSI Design and Test'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation
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    Chapter 2 A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier
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    Chapter 3 A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application
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    Chapter 4 Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit
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    Chapter 5 Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function
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    Chapter 6 Flexible Adaptive FIR Filter Designs Using LMS Algorithm
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    Chapter 7 An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB
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    Chapter 8 A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology
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    Chapter 9 A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip
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    Chapter 10 Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor
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    Chapter 11 Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology
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    Chapter 12 Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC
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    Chapter 13 Approximate Computing Based Adder Design for DWT Application
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    Chapter 14 An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits
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    Chapter 15 A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology
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    Chapter 16 On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting
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    Chapter 17 Utilizing NBTI for Operation Detection of Integrated Circuits
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    Chapter 18 A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS
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    Chapter 19 A CMOS Low Noise Amplifier with Improved Gain
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    Chapter 20 Radiation Hardened by Design Sense Amplifier
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    Chapter 21 Delay Efficient All Optical Carry Lookahead Adder
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    Chapter 22 Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit
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    Chapter 23 A Unified Methodology for Hardware Obfuscation and IP Watermarking
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    Chapter 24 Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance
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    Chapter 25 Brain Inspired One Shot Learning Method for HD Computing
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    Chapter 26 Dual-Edge Triggered Lightweight Implementation of AES for IoT Security
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    Chapter 27 2L-2D Routing for Buffered Mesh Network-on-Chip
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    Chapter 28 Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network
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    Chapter 29 An Ultra Low Power AES Architecture for IoT
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    Chapter 30 Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor
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    Chapter 31 Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects
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    Chapter 32 A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs
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    Chapter 33 ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements
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    Chapter 34 Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard
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    Chapter 35 Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods
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    Chapter 36 Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms
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    Chapter 37 Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
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    Chapter 38 A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata
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    Chapter 39 User Guided Register Manipulation in Digital Circuits
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    Chapter 40 RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor
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    Chapter 41 Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU
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    Chapter 42 Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things
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    Chapter 43 A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance
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    Chapter 44 Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop
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    Chapter 45 Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell
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    Chapter 46 A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications
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    Chapter 47 Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
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    Chapter 48 A Novel Design of SRAM Using Memristors at 45 nm Technology
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    Chapter 49 Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications
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    Chapter 50 An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit
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    Chapter 51 Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects
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    Chapter 52 A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell
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    Chapter 53 Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell
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    Chapter 54 Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications
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    Chapter 55 Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model
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    Chapter 56 Technology Characterization Model and Scaling for Energy Management
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    Chapter 57 GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET
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    Chapter 58 Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures
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    Chapter 59 Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap
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    Chapter 60 Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain
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    Chapter 61 A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes
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    Chapter 62 All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model
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    Chapter 63 Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem
Overall attention for this book and its chapters
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Title
VLSI Design and Test
Published by
Springer Singapore, January 2019
DOI 10.1007/978-981-32-9767-8
ISBNs
978-9-81-329766-1, 978-9-81-329767-8
Editors

Sengupta, Anirban, Dasgupta, Sudeb, Singh, Virendra, Sharma, Rohit, Kumar Vishvakarma, Santosh

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Geographical breakdown

Country Count As %
Unknown 1 100%

Demographic breakdown

Readers by professional status Count As %
Student > Master 1 100%
Readers by discipline Count As %
Engineering 1 100%