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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
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    Chapter 1 System-Level Application-Specific NoC Design for Network and Multimedia Applications
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    Chapter 2 Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements
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    Chapter 3 A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms
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    Chapter 4 An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture
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    Chapter 5 Template Vertical Dictionary-Based Program Compression Scheme on the TTA
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    Chapter 6 Asynchronous Functional Coupling for Low Power Sensor Network Processors
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    Chapter 7 A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs
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    Chapter 8 Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports
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    Chapter 9 The Design and Implementation of a Power Efficient Embedded SRAM
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    Chapter 10 Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN
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    Chapter 11 Settling Time Minimization of Operational Amplifiers
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    Chapter 12 Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs
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    Chapter 13 Computation of Joint Timing Yield of Sequential Networks Considering Process Variations
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    Chapter 14 A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation
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    Chapter 15 A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
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    Chapter 16 A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect
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    Chapter 17 Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components
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    Chapter 18 Logic Style Comparison for Ultra Low Power Operation in 65nm Technology
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    Chapter 19 Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation
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    Chapter 20 Clock Distribution Techniques for Low-EMI Design
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    Chapter 21 Crosstalk Waveform Modeling Using Wave Fitting
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    Chapter 22 Weakness Identification for Effective Repair of Power Distribution Network
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    Chapter 23 New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses
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    Chapter 24 On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects
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    Chapter 25 Soft Error-Aware Power Optimization Using Gate Sizing
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    Chapter 26 Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices
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    Chapter 27 RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating
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    Chapter 28 Functional Verification of Low Power Designs at RTL
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    Chapter 29 XEEMU: An Improved XScale Power Simulator
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    Chapter 30 Low Power Elliptic Curve Cryptography
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    Chapter 31 Design and Test of Self-checking Asynchronous Control Circuit
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    Chapter 32 An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips
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    Chapter 33 Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA
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    Chapter 34 Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform
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    Chapter 35 The Energy Scalability of Wavelet-Based, Scalable Video Decoding
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    Chapter 36 Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
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    Chapter 37 Exploiting Input Variations for Energy Reduction
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    Chapter 38 A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates
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    Chapter 39 Static Power Consumption in CMOS Gates Using Independent Bodies
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    Chapter 40 Moderate Inversion: Highlights for Low Voltage Design
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    Chapter 41 On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems
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    Chapter 42 Semi Custom Design: A Case Study on SIMD Shufflers
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    Chapter 43 Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
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    Chapter 44 Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS
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    Chapter 45 A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits
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    Chapter 46 Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates
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    Chapter 47 A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning
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    Chapter 48 Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems
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    Chapter 49 Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate
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    Chapter 50 A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations
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    Chapter 51 Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data
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    Chapter 52 Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply
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    Chapter 53 Low-Power Digital Filtering Based on the Logarithmic Number System
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    Chapter 54 A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
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    Chapter 55 Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers
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    Chapter 56 Design and Industrialization Challenges of Memory Dominated SOCs
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    Chapter 57 Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies
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    Chapter 58 Analog Power Modelling
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    Chapter 59 Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms
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    Chapter 60 System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters
Overall attention for this book and its chapters
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Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer Berlin Heidelberg, August 2007
DOI 10.1007/978-3-540-74442-9
ISBNs
978-3-54-074441-2, 978-3-54-074442-9
Editors

Azémard, Nadine, Svensson, Lars

Mendeley readers

The data shown below were compiled from readership statistics for 52 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Germany 2 4%
Italy 1 2%
India 1 2%
France 1 2%
Spain 1 2%
Mexico 1 2%
United Kingdom 1 2%
Belgium 1 2%
Hungary 1 2%
Other 1 2%
Unknown 41 79%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 24 46%
Student > Master 9 17%
Researcher 4 8%
Professor > Associate Professor 3 6%
Student > Doctoral Student 3 6%
Other 9 17%
Readers by discipline Count As %
Engineering 30 58%
Computer Science 20 38%
Physics and Astronomy 1 2%
Business, Management and Accounting 1 2%