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Mendeley readers
Chapter title |
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms
|
---|---|
Chapter number | 3 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2007
|
DOI | 10.1007/978-3-540-74442-9_3 |
Book ISBNs |
978-3-54-074441-2, 978-3-54-074442-9
|
Authors |
Ioannis Panagopoulos, Christos Pavlatos, George Manis, George Papakonstantinou |
Mendeley readers
The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 3 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor | 1 | 33% |
Professor > Associate Professor | 1 | 33% |
Other | 1 | 33% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 3 | 100% |