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Mendeley readers
Chapter title |
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect
|
---|---|
Chapter number | 16 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2007
|
DOI | 10.1007/978-3-540-74442-9_16 |
Book ISBNs |
978-3-54-074441-2, 978-3-54-074442-9
|
Authors |
Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie |
Mendeley readers
The data shown below were compiled from readership statistics for 18 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Iraq | 1 | 6% |
Hong Kong | 1 | 6% |
United States | 1 | 6% |
Unknown | 15 | 83% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Student > Ph. D. Student | 5 | 28% |
Student > Doctoral Student | 4 | 22% |
Researcher | 3 | 17% |
Student > Master | 1 | 6% |
Professor | 1 | 6% |
Other | 0 | 0% |
Unknown | 4 | 22% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 10 | 56% |
Computer Science | 2 | 11% |
Materials Science | 1 | 6% |
Physics and Astronomy | 1 | 6% |
Unknown | 4 | 22% |