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Mendeley readers
Chapter title |
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations
|
---|---|
Chapter number | 50 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2007
|
DOI | 10.1007/978-3-540-74442-9_50 |
Book ISBNs |
978-3-54-074441-2, 978-3-54-074442-9
|
Authors |
Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti |
Mendeley readers
The data shown below were compiled from readership statistics for 4 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Germany | 1 | 25% |
Unknown | 3 | 75% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor | 1 | 25% |
Professor > Associate Professor | 1 | 25% |
Researcher | 1 | 25% |
Student > Master | 1 | 25% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 3 | 75% |
Biochemistry, Genetics and Molecular Biology | 1 | 25% |